Electronic plugboard controlled data processor

ABSTRACT

An electronic processing unit having solid state components and including a punched card reader, printer and punch output, and plugboard program for controlling the operations of start, stop, read, add, subtract, compare, insert, delete, print, punch, etc. The processor can perform the operations of transfer of information, add, compare, and edit. It can use 80-, 90-, or 160column cards.

United States Patent Breslin et a1. 5] June 13, 1972 [54] ELECTRONICPLUGBOARD [56] References Cited CONTROLLED DATA PROCESSOR UNITED STATESPATENTS Ihvemors= y Anne Breslin, Philadelphia; George 2,493,858 1 1950Carroll et al., ..235 61.8 R. Cogar, Doylestown. both of 2,615,629 /1952Dayger et al... ..235/6l9 Charles A. Lee, Stamford, Conn.; Donald3,035,764 5/1962 Beman 235/61 9 O. Neddenriep, Willow Grove; Albert J.2,973,141 2/1961 Berezin.... .235/61 9 Romeo, Springfield, both of Pa.;Ernesto 2,907,526 lO/ 1959 Havens.... ..235/174 G, Saving, New YorkTorkje" 2,910,240 Havens...: ..235/l74 Sekse, Norristown, Pa.

Primary Eraminer-Daryl W. Cook Asslghw Sperry Rand Corporahon, New York,Attorney-Charles c. English, William E. Cleaver and Charles E. McTiernan[22] Filed: June 18, 1962 ABSTRACT [21] Appl' 203071 An electronicprocessing unit having solid state components and including a punchedcard reader, printer and punch out- 52 us. c1 ..235/6l.9, 340/1725 p andp gbo p g for controlling the operations of 51] Int. Cl- ..G06f 7/12,G06f7/00,G06f /00 Start, p, read, subtract, compare, insert, delete, p

[58] Field ofSearch ..235/61.6 R,6l.9 R; 340/1725 Punch, etc. TheProcessor can Perform the operations of MFMORY MAR (OM/ ARA transfer ofinformation, add, compare, and edit. It can use or column cards.

21 Claims, 438 Drawing Figures F01, F62, F63, (0/1 7804 04TH R M E E 0 6M A a 7 5 TRANSLATE A R A T 90 x53 0 Y E p R A (C A ACC R w e a MEMOR ywsnwcrm/V 'p/I' CON/7M4 PRCEDE/VCE (WA/7790A 1 9 1 l /6o/9o 55 957P/e/Nrfl? FKTENTEBJuu 13 m2 SHEET 03 OF 184 l rl PATENTEUM 13 2972 SHEET05 OF 184 70 Cal.

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1. Plugboard controlled data processor comprising in combination:magnetic core memory means having a plurality of locations; plugboardmeans providing means to transmit signals therefrom and means to receivesignals therein; counter means for sequentially generating a pluralityof programs signals, said counter means connected to said plugboard toprovide said program signals thereat; plurality of gate circuits eachhaving control input means connected to certain of said means to receivesignals on said plugboard; memory addressing circuitry connected to saidmagnetic core memory and to said gate circuits for selectively enablingwrite-in and read-out of information to and from said memory; firstregister means connected to said memory to receive information therefromand to transmit information thereto; second register means; thirdregister means; comparison circuitry connected to said first registermeans and said second register means to make comparison betweeninformation held respectively thereat; circuitry means connecting thesaid third register means to said second register means to receiveinformation therefrom; arithmetic means connected to said secondregister and to said first register to receive information therefrom andto operate thereon, said adder means further having circuitry meansconnecting the output therefrom to said first register means; andcircuitry means connecting said adder means and said memory means andsaid gate circuits to the said plugboard means to receive the commandsignals therefrom.
 2. A plugboard controlled processor comprising incombination: magnetic core memory means having a plurality of locationsfor storing information; punched card reader means; addressing meansconnected to said memory means for selecting any particular location insaid memory means; logic circuitry means connecting said punched cardreader to said addressing means for transmitting informationtherethrough to be stored in said memory from said punched card reader;buffer means connected to said memory means for receiving informationtherefrom and transmitting information thereto; circuit means foraffecting information transmitted from said memory means connected tosaid buffer means; said punched card reader formed to accept informationfrom punched cards in three different codes; translation means in saidcard reader for automatically translating said three codes into twodifferent machine codes in order for such information to be processed;and plugboard means connected to said magnetic core memory, to saidlogic circuitry means, to said circuit means for affecting information,to said punched card reader input means so that when signals are routedby said plugboard, information can be read from said punched card readerand thereafter transmitted through said memory to be acted upon andreturned thereto.
 3. An asynchronous, plugboard controlled processorcomprising in combination: magnetic core memory means having a pluralityof locations each capable of storing n bits of information where n bitsof information represent a word; addressing means connected to saidmagnetic core memory means to enable any selected ones of said locationsto be activated to receive or transmit information; card reader inputmeans; card punch output means; printer output means; first logiccircuitry means connecting said memory means to said card punch outputmeans and to said printer output means; first circuitry means connectingsaid card reader input means to said addressing means and to said firstlogic circuitry means; plugboard means having means to route commandsignals and means to address the least significant and most significantlocations of an operand stored in said memory means and connected tosaid card reader means, to said printer means, to said punch outputmeans and to said first logic circuitry means whereby an operand can bestored into or extracted from said memory which can be any number ofbits in length up to the capacity of the memory to be used in saidprocessor; program counter means for sequentially initiating a pluralityof program signals connected to said plugboard means to provide saidprogram signals thereat; arithmetic means for performing arithmeticoperations on information transmitted thereto connected to saidplugboard means; second circuitry means connecting said arithmetic meansto said first logic circuitry means; and instruction control signalmeans connected to said plugboard means and further circuitry connectedto said first logic circuitry means whereby when said plugboard means iswired to transmit signals from said program counter means to said firstlogic circuitry means and to said instruction control signal means andto any one or all of said reader input means, said punch output means onsaid printer output means said processor will operate to receiveinformation into said memory and transmit information out of said memoryfor purpose of having said information operated arithmetically thereonin accordance with instruction control signals generated in response tothe routing of command signals on said plugboard.
 4. A plugboardcontrolled processor to be used with punched cards which may haveinformation coded thereon in one of three different card codescomprising in combination: memory means having a plurality of memorylocations; addressing means connected to said memory means to enableparticular ones of said locations to be activated to receive or transmitinformation; said plugboard means having output means and having meansto address the least significant and most significant locations of anoperand stored in said memory means connected to said addressing meanswhereby an operand of any variable length can be processed through saidmemory; punched card reader means having control circuitry connected tosaid plugboard means; storage address circuitry means connected to saidpunched card reader means and to said magnetic core memory means andformed to direct information from said punched card reader means to saidmagnetic core memory means in one of two machine codes depending uponwhich of said three different card codes is present on a card being readand said storage address circuitry means further formed to direct saidinformation to preselected memory locations in accordance with the typeof machine code present on said punched cards being read by said punchedcard reader means; program signal source means connected to output meanson said plugboard means in order to provide program signals thereto,whereby when said plugboard is wired from said output means to saidcontrol circuitry of said punched card reader, information will besupplied to said memory in response to said punch card readertransmitting the same.
 5. A plugboard controlled processor according toclaim 4 wherein said program signal source means includes a programcounter formed to sequentially generate program signals to said outputmeans on said plugboard means and further includes a program countercontrol means connected to said program counter and to said plugboardmeans and formed to start said program counter at any desired count atthe start of processor operation and alternatively at the end of anyregularly occuring program step in response to signals applied to saidplugboard means.
 6. A plugboard controlled processor according to claim5 and further including: circuitry for performing arithmetic, logicaland edit operations; first circuitry means connecting said circuitry forperforming arithmetic, logical and edit operations to said plugboardmeans and to said magnetic core memory means; first control circuitrymeans connected to said circuitry for performing arithmetic, logical andedit operations and to said plugboard means; printer output means; cardpunch output means; and precedence control circuitry connected to saidprinter output means, to said card punch output means and to saidaddressing means to make a determination of the precedence amongst saidpunched card reader, said printer output means and said card punchoutput means in order that an operation of each can be performed on asingle program step.
 7. A plugboard controlled processor comprising incombination memory means having a plurality of locations; addressingmeans connected to said memory means; plugboard means having input meansconnected to said addressing means to select the positions in saidmemory means for the most significant location as well as the leastsignificant location for a first operand and the most significantlocation and the least significant location for a second operand each ofsaid operands being selected variable in length; memory data registermeans connected to said memory means for accepting information signalstherefrom for temporarily storing said information signals; and sequencecontrol means connected to said addressing means and to said plugboardmeans and formed to cause said addressing means to sequentially activatememory locations within said memory means according to a pattern whichgoes from a least significant location to a most significant locationand alternatively according to a pattern which goes from a mostsignificant location to a least significant location.
 8. A plugboardcontrolled processor according to claim 7 wherein there is furtherincluded a comparison circuit means connected to said addressing meansand to said sequence control means to compare the address defined atsaid plugboard input means with the address currently activating saidmemory means in order to provide an ending address when the memorylocations being activated coincide with the memory locations defined onsaid plugboard means.
 9. A programmed controlled processor according toclaim 8 wherein there is further included second control circuitryconnected to said comparison circuit and to said addressing means toprevent the comparison of the memory locations activated with theaddress of said first operand as defined on said plugboard means afterthere has been an identity between the ending address of said secondoperand and the activated memory locations.
 10. A plugboard controlledprocessor according to claim 7 wherein said sequence control meansinclUdes first and second counters, a comparison means and first andsecond logic circuitry, and wherein said plugboard means has commandsignal input means wired and wherein said first logic circuitry connectssaid first counter to said plugboard means so that the starting addressof an operand can be transferred from said plugboard to said firstcounter and thereafter to said addressing means and whereby the endingaddress of the first operand can be transferred from said plugboard tosaid first counter and thereafter to said comparison means wherebycomparison will be made between the starting address of said firstoperand and the ending address of said first operand and if there is nocomparison said information is returned to said first counter meanswhere it is decremented and alternatively incremented depending uponwhether a command signal is an ascending or a descending transfer, andfurther whereby the starting address of a second operand is transferredthrough said second counter to said addressing means and the endingaddress of a second operand is transferred thereafter through saidsecond counter to said comparison means and whereby after a comparisonhas been made if there is no comparison said information in saidaddressing means is returned to said second counter and either increasedor decreased depending upon whether the command signal is an ascendingor a descending transfer.
 11. A plugboard control processor comprisingin combination: memory means having a plurality of locations eachcapable of storing n bits of information; addressing means connected tosaid memory means to enable particular ones of said locations to beactivated to receive or transmit information; plugboard means providinginput means to select the positions in said memory means for the mostsignificant location and the least significant location for a firstoperand as well as the most significant location and a least significantlocation for a second operand, said operands being variable in length;memory data register means connected to said memory means to acceptinformation therefrom and return information thereto; first accumulatormeans connected to said memory data register means; second accumulatormeans connected to said first accumulator means; adder means connectedto said first accumulator means and said second accumulator means andfurther connected to return information to said memory data register;control circuitry means connected to said memory data register and saidaddressing means for selecting information from said memory to betransferred to said memory data register and further connected to saidfirst and second accumulators to transfer information from said memorydata register respectively into said first and second accumulators;circuitry means connecting said adder means to said plugboard means toenable said adder means to receive information from said first andsecond accumulators for the purpose of performing an arithmeticoperation thereon; and further control circuitry means connected to saidcircuitry means connecting said adder to said memory data register tocause the information in said adder means to be transferred to saidmemory data register for a further transfer therefrom to said memorymeans.
 12. Plugboard control processor according to claim 11 whereinthere is further included a comparator means connected to said memorydata register and to said first accumulator whereby information which istransferred to said first accumulator and second information which istransferred to said memory data register can be compared to generate acontrol signal to initiate a further logic operation on saidinformation.
 13. A plugboard control processor according to claim 11wherein there is further included edit control means connected to saidplugboard means and to said memory data register and wherein there isfurther included instruction control circuitry, said instruction controlcircuitry connected to said plugboard whereby when said plugboardprOvides a command signal to said edit control circuitry andalternatively wherein said instruction control circuitry provides acommand signal to said edit control circuitry whereby the information insaid memory data register is edited before it is transmitted therefrom.14. A plugboard control processor comprising in combination: a memorymeans having a plurality of locations; memory access control meansconnected to said memory means for selectively enabling the write-in orread-out of information from chosen ones of said plurality of locations;temporary storage means connected to said memory means for receivinginformation therefrom and returning information thereto; arithmeticmeans connected to said temporary storage means for performingarithmetic functions upon information transmitted from said selectedones of said plurality of storage locations; punched card reader inputmeans connected to said memory access control unit for transferringinformation into said memory through said memory access control unit;printer output means connected to said temporary storage means forreceiving information therefrom; and plugboard means having input meansconnected to said memory access control means to select positions insaid memory means for the most significant locations as well as theleast significant locations of operands which are processed andconnected to said memory means, to said memory access control means, tosaid punch card reader input means, to said printer output means, and tosaid arithmetic means for providing command signals thereto to enableinformation to be read from said punched card reader input means intosaid memory wherefrom it is transmitted to have an arithmetic operationperformed thereon and returned to said memory as well as to said printeroutput.
 15. A plugboard controlled processor comprising in combination:memory means having a plurality of locations; memory address circuitryconnected to said memory means for selectively enabling the read-out andwrite-in of information from and to any particular ones of saidlocations thereby enabling operands to be variable in length for anynumber of bits up to the capacity of said plurality of locations;temporary storage means connected to said memory means to receiveinformation therefrom and transmit information thereto; punched cardinput means connected to said memory address circuitry; printer outputmeans connected to said temporary storage means; first circuitry meansfor performing arithmetic, logical, transfer, insert, and deletionoperations and information transmitted from said temporary storagemeans; instruction input means coupled to said first circuitry means forenabling individual instructions to be formed by said first circuitrymeans; program counter formed to generate a plurality of initiatingsignals; selective circuitry means connecting said program counter tosaid instruction input means for selectively initiating instructionstherethrough; means for changing the sequence of said initiating signalsconnected to said program counter and adapted to be connected to saidselective circuitry means in order to enable said processor toselectively change said sequence of instruction; control circuitry meansconnected to said punch card input means and said printer output means;and execute order means connected to said control circuitry and adaptedto be connected to said selective circuitry means whereby said controlcircuit enables said punch card input means and printer output means toperform certain instructions only upon receipt of an execute order fromsaid selective circuitry means.
 16. The processor defined in claim 15wherein a first group of said memory locations are assigned for use bysaid reader and connected to said memory address circuitry, equal innumber to the maximum number of units of information able to be derivedfrom a punched card; a second group of memory locations are assigned foruse by said printer and connected to said memory address circuitry,equal in number to the maximum number of units of information able to beprinted on a single line; control circuitry connected from said readerand said printer to said memory address circuitry for controlling saidmemory address circuitry to access each of their assigned memorylocations respectively upon receipt of an execute instruction followingreceipt of a print order or read order instruction; and earlytermination circuitry associated with and connected to each said readerand said printer for terminating said access of their said assignedmemory locations after a given number of locations less than saidassigned number of locations have been accessed.
 17. The processordefined in claim 16 wherein early termination circuitry includes a firstregister means for temporarily storing an address defining the memorylocation ending accessed, a second register means for storing an addressfrom said instruction input means defining the last memory location tobe accessed; and means for comparing connected to said first and saidsecond register to compare the contents of said first and secondregisters and provide an output signal upon coincidence of saidrespective first and second register contents, and circuitry meansconnecting an output from said comparing means to said memory addresscircuitry for terminating instruction then being executed.
 18. A dataprocessor comprising in combination a memory device having a pluralityof separate memory locations; address circuit means connected to saidmemory device for selectively writing in and reading out any number ofchosen ones of said memory locations; punched card reader input meansconnected to said memory address circuit and including a translationcircuit; circuitry means connected to said translation means forderiving information from cards passed through said punch card reader insaid first, second or third codes and transferring said information tosaid predetermined ones of said memory locations into first or secondmachine codes; temporary storage means connected to said memory meansfor receiving information therefrom and transmitting informationthereto; printer output means connected to said temporary storage meansfor printing information received therefrom without translation; firstcircuitry means connected to said temporary storage means to performarithmetic, logical, transfer, insertion or deletion operations andinformation being processed in said processor; sequencing signal meansconnected to said memory address circuit means for sequentially enablinga plurality of memory locations of said memory means; and plugboardmeans connected to said first circuitry means, to said printer outputmeans, to said punch card reader means, to said memory address circuitmeans, to said memory means whereby instruction signals provided by saidplugboard means can cause information to be transmitted from said punchcard reader to said memory means through said temporary storage to saidfirst circuitry means back to said temporary storage and to said printeroutput means to provide an output therefrom.
 19. A data processoraccording to claim 18 wherein there is further included a card punchunit connected to said temporary storage means and formed to operate ina row by row or column by column manner; second logic circuitry meansconnecting said plugboard means to said address circuit means to causethe latter to access said memory device in a first mode when said cardpunch unit is operating row by row and in a second mode when said cardpunch unit is operating column by column.
 20. A data processor accordingto claim 19 wherein said card punch unit is formed to punch cardsaccording to first, second and third modes each of which is differentand wherein said second logic circuitry is formed to selectivelycondition said memory address circuit to access different portions ofsaid memory for each of said different codes.
 21. A data processoraccording to claim 18 wherein there is further included memoRyprecedence circuitry connected to said printer output means and to saidcard punch unit and wherein said memory precedence circuitry isconnected to said second logic circuitry to determine the order ofpriority of operations between said printer output means and said punchoutput unit.